The present invention relates to phase lock loop (PLL) circuits and methods, and more particularly to a PLL circuit and method in which the lock point of the PLL is not fixed so that the phase between adjacent samples may be advanced a value from 0 to 2.pi..
Conventional PLL circuits lock on a particular lock point that is fixed. The phase between adjacent samples can be advanced by a single value, 2.pi.. In synthesizers and modulators this limitation is desirably eliminated so that a PLL circuit lock point can be advanced in steps of from 0 to 2.pi. without changing the reference frequency (RefClk), and so that the loop bandwidth (B.sub.3dB), the natural frequency .omega..sub.n, and the dampening .zeta. are independent of the output frequency (fout).
Present synthesizers and modulators employ techniques in which a conventional PLL circuit is phase locked to a direct digital synchronizer (DDS) either through a down conversion or a divide-by. The down conversion technique typically provides a narrow band PLL, while the divide-by technique has problems with phase noise multiplication. Neither technique provides the rapid acquisition and small step sizes that are desired in synthesizers and modulators, while maintaining low phase noise and large tuning ranges.
Accordingly, it is an object of the present invention to provide a novel PLL circuit and method that obviate the problems of the prior art.
It is another object of the present invention to provide a novel PLL circuit and method for a synthesizer/modulator in which the DDS is eliminated.
It is yet another object of the present invention to provide a novel PLL circuit and method for locking on a predetermined frequency and phase, the phase having a value from 0 to 2.pi. that need not be constant.
It is still another object of the present invention to provide a novel PLL circuit and method for locking on a predetermined frequency and phase in which phase noise is reduced.
It is a further object of the present invention to provide a novel PLL circuit and method in which frequency and/or phase error corrective signals are averaged before being provided to an oscillator.
It is still a further object of the present invention to provide a novel phase detector for converting an analog signal from an oscillator to digital signals related to the phase of the analog signal.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.